The present disclosure relates generally to multilayer semiconductor structures, and more specifically, relates to forming high quality multilayer stacks for 3D vertical gate (VG) NAND devices.
Semiconductor device manufacturers continue to seek ways to shrink critical dimensions of semiconductor devices and achieve greater storage capacity in smaller areas and at lower costs per bit.
Recent developments include forming three-dimensional (3D) semiconductor devices using thin film transistor (TFT) techniques applied to charge trapping memory techniques, and cross-point array techniques applied for anti-fuse memory. In respect to the latter, multiple layers of word lines and bit lines are provided with memory elements at their respective cross-points. Developments also include forming vertical NAND cells using charge-trapping memory technology, in which a multi-gate field effect transistor structure having a vertical channel operating like a NAND gate uses silicon-oxide-nitride-oxide-silicon (SONOS) charge trapping technology to create a storage site at each gate/vertical channel interface. In respect to the latter, recent developments have improved the size and manufacturing costs for three-dimensional semiconductor devices by forming stacks of strips of conductive material separated by insulating material and providing memory elements in interface regions between conductive materials of the stacks.